An important function in modern signal processing is that of converting an analog signal into a digital representation. This function is accomplished by sampling the analog signal at periodic intervals and then quantizing the value of the time sampled analog signal into discrete values. A more accurate digital representation is obtained by taking more samples over a given amount of time, which implies a faster sampling rate or sampling frequency fS.
Any signal having a frequency component fC that is greater than half the sampling frequency will be corrupted during the sampling process. The distortion of signals having frequency components fC greater than half the sampling frequency (i.e., at fS/2) is called aliasing. Aliasing is an inherent sampling phenomenon and results in frequency components above half the sampling frequency being converted into frequency components below half the sampling frequency according to the equation fA=(fSxe2x88x92fC). Aliasing does not change frequency, components less than half the sampling frequency. Aliasing is typically reduced by filtering out frequencies at and above half the sampling frequency (fS/2) before sampling. This avoids corrupting low frequency content with aliased high frequency content at the expense of losing the high frequency information.
Fundamental analog issues such as settling time present another problem in the digitization of an analog signal. For any given digitization system, the accuracy requirement placed on the design limits the maximum sampling rate and thus the non-aliasing bandwidth of the system. Different digitization technologies will exhibit different accuracy vs. sampling rate curves, but an inverse relationship always exists between accuracy and sampling rate. If greater accuracy is desired, the design will be limited to a smaller bandwidth. In other words, a faster digitization system (greater bandwidth) will be limited to less accuracy than will be a slower digitization system (less bandwidth) for a given conversion technology.
In the common measurement application of signal power estimation, the measurement bandwidth of the analog-to-digital converter (ADC) places a limit on the over-all system bandwidth. In this application a need typically exists for higher accuracy at lower frequencies. For power estimation, there are two typical approaches for measuring signals that exceed the raw system ADC bandwidth. The first solution uses some type of analog RMS converter such as a log-antilog IC or a thermal transducer to convert the input signal into a low bandwidth signal whose value is proportional to the input signal power. This system can be expensive, is limited by the converter accuracy, and cannot measure signal characteristics such as maximum or minimum. The second method requires the input to be periodic and uses a track-and-hold circuit with a synchronous triggering system and a high accuracy analog-to-digital converter to sub-sample the input signal. While this solution can be very accurate, it is strictly limited to periodic inputs and is both costly and complex.
For general digitizing applications wherein the system analog-to-digital converter cannot simultaneously meet the necessary bandwidth and accuracy, there are also two common techniques in use. The first solution uses two analog-to-digital converters. The sampled signal stream of either one or the other is used depending on the system configuration. This solution can be expensive and forces an explicit mode change that generally introduces a discontinuity in the trade-off between reading rate and accuracy. The second solution uses a sub-sampling system similar to that used in power estimation and suffers from the same set of drawbacks.
In representative embodiments, a dual path analog-to-digital conversion method and system is described. The system includes a first and second circuits. The first and second circuits each convert an input analog signal into digital signals at differing sample rates. The circuit having the slower sampling rate aliases frequency components of the input analog signal that are higher than twice that sampling rate. Frequency components that are aliased in the slower sampling circuit are replicated from the faster sampling circuit at the appropriate amplitude, intentionally folded into the aliased frequency via a down-sampling operation, and subtracted from the output of the slower sampling circuit. The outputs of both sampling circuits are then merged.
The overall sampling rate of a given low-frequency analog-to-digital system can be increased without reducing the low frequency accuracy. In representative embodiments, a second, faster analog-to-digital converter is added to a first, slower converter. The faster converter has a lower accuracy than that of the slower converter but has a higher sampling rate. The two sample data streams are then merged. The resulting dual path analog-to-digital converter has an increased sampling rate but the same low frequency accuracy as the slower analog-to-digital converter.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.